1. Technical Field
The disclosure relates generally to patterning of semiconductor structure in complementary metal oxide semiconductor (CMOS) circuits fabrication, and more particularly, to method of enhancing a patterned hard mask.
2. Background Art
In the current state of the art, continued complimentary metal oxide semiconductor (CMOS) scaling has resulted in high density CMOS circuitry. Optical effects in the printing of patterns onto substrates of semiconductors for CMOS circuitry fabrication lead to rounding and dimensional reduction at the ends of printed lines. Often, the rounding and dimensional reduction exacerbates the effectiveness of device and circuit operations in a densely packed circuitry. This is demonstrated in 45 nm static random access memory (SRAM) designs at the active area (RX) and polycrystalline layers.
Crystallographic etching has been recognized as a means for enhancing printed patterns at the RX level. The use of this type of etching technique requires a monocrystalline layer. However, as most semiconductor structures involve non-crystalline and polycrystalline layers, the use of crystallographic etching for such enhancement purposes cannot be applied directly to every level of semiconductor fabrication.